Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36.
The three-dimensional vertical NAND strings can be formed by forming an alternating stack of insulating layers and sacrificial material layers, and by replacing the sacrificial material layers with electrically conductive layers. Formation of voids during formation of the electrically conductive layers due to non-conformity can lead to electrical failures and/or structural instability of the three-dimensional NAND strings.